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Mono- and Multi-crystalline wafer lifetime measurement device
State of the art system for topographic electrical characterization of multicrystalline bricks in fabs with high throughput....
Production integrated high speed wafer mapping of carrier lifetime. Single wafer topograms in less than one second a wafer.
Low cost table top lifetime measurement system for characterization of a variety of different silicon samples at different...
Mono- and Multi-crystalline wafer and brick lifetime measurement device
Flexible OEM unit for lifetime measurements at a variety of different samples ranging from mono- to multicrystalline silicon...
Microwave Detected Photo Induced Current Transient Spectroscopy
The minority carrier life time is sensitive for all kinds of electrically active defects in semiconductors and is therefore...
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benchtop PID test for solar wafers and mini-modules
portable in field PID tester for solar modules
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The PIDcon devices are designed to investigate the PID susceptibility for production monitoring of solar cells as well as tests...
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For ultra-fast crystal orientation and rocking curve measurements
Flexible diffractometer for ultra-fast Omega Scan orientation determination
Smart diffractometer for ultra-fast Omega-scan of small samples.
Robust XRD equipment for fully automated in-line testing & alignment
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discover the most convenient way of measuring orientation of single crystals
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Potential induced degradation (PID) is one of the most dangerous degradation phenomena observed in c-Si modules. Great progress has been achieved in the understanding of the basic mechanism of PID of the shunting type (PID-s).
In the field a large potential between the front glass surface and the solar cells in a module can occur and a shunting of the p-n junction of a Si solar cell and accordingly a decrease in resistance and power output can be caused.
The following model was proposed by :The high field strength present in the modules causes a Na+ drift through the SiNx layer. The Na ions diffuse laterally at the SiNx/Si interface (SiOx) and decorate the stacking faults. The pn-junction is shunted through a hopping process via defect levels of the highly decorated stacking fault (process 1) and additionally the J02 increases due to recombination processes via defect states in the depletion region (process 2). Note that the Na ions are supposed to originate from the Si surface and not the glass.
Hence the susceptibility of a module depends mostly on the SiNx layer and the resistivity of the glass and the EVA foil.
For more information, please read: V. Naumann et al., The role of stacking faults for the formation of shunts during potential induced degradation (PID) of crystalline Si solar cells, Phys. Stat. Solidi RRL 7, No. 5 (2013) 315-318